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Increased operating temperatures of chips have aggravated leakage and reliability issues, both of which are adversely affected by high temperature. Due to thermal diffusion among IP-blocks and the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a system on chip (SoC). An increase in temperature...
Summary form only given. Improvements in the speed and the size of chips due to process scaling come with the penalties of increased power densities and higher operating temperatures. Higher temperature not only poses a risk of thermal runaway of the chips but also increases leakage-power dissipation and reduces interconnect lifetime. Furthermore, the floorplan of a System-on-a-Chip (SoC) has a significant...
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