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Recent publications have demonstrated ADCs with ENOB > 11, sampling frequencies > 50MHz, with power < 50mW, making the SAR ADC architecture an attractive alternative to the traditional pipeline. This paper presents a production quality 11.5 ENOB, 89dB SFDR, 100MS/s SAR ADC that, including the voltage reference and digital calibration circuitry, consumes 8mW and uses 0.1mm2 in 28nm CMOS. It...
A dual-channel 10b 80MS/s low-power and area-efficient pipeline ADC is presented. Area and power savings are realized by merging the track and hold amplifier (THA) and the 1st-stage multiplying digital-to-analog converter (MDAC), double-sampling the 2nd-stage MDAC and using a 1b sub-range in 4b sub-ADC. It achieves an ENOB of 8.65b with 20.1-MHz input. Including on-chip reference buffers, power and...
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