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This paper describes a single-chip, 2 × 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1:4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax...
In this paper, a sample-and-hold circuit for a reconfigurable ADC is presented. This design is based on TSMC 0.18µm process. Flip-around architecture is employed to implement overall circuit which may contribute to low noise and fast settling with consuming lower power. To achieve high linearity, improved bootstrapped switches are introduced in this design. A fully differential folded-cascode OTA...
A 40 Gbps optical receiver analog front end integrating a trans-impedance amplifier (TIA) and a limiting amplifier is presented. To achieve wide band operation, nested feedback TIA and interleaving post amplifier with split series-peaking are proposed in this design. This receiver provides the transimpedance of 92 dBOhm, input-referred noise of 14 pA/√Hz, −3dB bandwidth of 35 GHz, and 800mVpp differential...
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