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This paper proposes a new watermarking scheme for intellectual property (IP) protection of sequential circuits. The method embeds the watermark by encoding the state variables as opposed to modifying the states and edges of state-transition graph (STG) in conventional finite state machine (FSM) watermarking schemes. It has the merits of being applicable to gate-level implementation of sequential circuit...
An area-efficient diminished-1 modulo 2n+1 multiplier with radix-4 modified Booth encoding is proposed. The proposed approach minimizes the number of Booth encoder and Booth decoder blocks required for partial product generation. Its correction factor is decomposed into a multiplier-dependent dynamic bias and a multiplier-independent static bias. The dynamic bias can be generated by hardwiring the...
Multiplication by one or several constants is a frequently required arithmetic operation in many DSP functions. A fast and low power implementation for single constant multiplication based on Canonical Signed Digit (CSD) was proposed by Pai et al. to extend it for multiple constant multiplication, two upper bounds for the number of partial product rows were derived. The general upper bound depends...
Hard multiple generation is the bottleneck operation in radix-8 Booth encoded modulo 2n - 1 and modulo 2n + 1 multipliers. In this paper, fast hard multiple generators for the moduli 2n - 1 and 2n + 1 are proposed. They are implemented as parallel-prefix structures based on the simplified carry equations. Synthesis results based on TSMC 0.18μm, 1.8V CMOS standard-cell library show that the proposed...
High-speed modulo multipliers are essential elements in RNS datapath. Booth recoding algorithm can be used to improve the performance of the multiplier by reducing the number of partial products. In radix-8 booth encoding, the number of partial products is reduced to one-third. However, the inevitable carry propagation adder required to generate the hard multiple, 3X, where X is the multiplicand,...
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