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A 648 MHz 153.8 mm2 45 nm CMOS SoC integrates eight general-purpose CPUs, four dynamically reconfigurable processors, two 1024-way matrix-processors, peripherals and interfaces. Using core enhancement, DDR3-I/F improvement and clock buffer deactivation, this SoC achieves 37.3 GOPS/W at 1.15 V.
This paper presents the first published single-chip RF tuner / OFDM demodulator for a mobile digital TV application (1-segment broadcasting). To improve the minimum sensitivity, spurious signal suppression techniques are proposed. The single-chip RF tuner / OFDM demodulator using the proposed spurious signal suppression techniques is fabricated using 90 nm CMOS technology and total die size is 3.26...
This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC)...
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