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Dynamic power reduction techniques such as sequential clock-gating aim at eliminating inconsequential computation and clock-toggles of the registers. Usually sequential clock-gating opportunities are discovered manually based on certain characteristics of a design (e.g. pipelining). Since manual addition of sequential gating circuitry might change the functionality of the design, sequential equivalence...
Managing power consumption in a System-On-Chip (SoC) design is becoming increasingly important. SoCs generally consist of various co-processors. Accurate power estimation of these co-processors at the highest possible abstraction level helps in performing early power-aware design tradeoffs. This paper presents a methodology to create abstract statistical power models for hardware co-processors and...
Advent of ldquosystem on chiprdquo technology has redefined the consumer electronics industry. The main advantage of such SoC based systems is cost and space effectiveness. Such systems are available for very cheap cost, which can be further used for some practical purposes with little effort, hence very practical solution for the applications such as protective relays. In this paper a ldquoUniversalrdquo...
Accurate and efficient power estimation at higher-levels of abstraction is becoming increasingly important. However, tools and methodologies are lacking for such a task. In this paper, we present a methodology for accurate power estimation at high-level by reusing pre-existing verification or validation resources in the design flow. This novel methodology enables architectural exploration and design...
Embedded systems are becoming complex day by day and their increasing demand with shorter time-to-market is forcing designers to migrate to electronic system-level (ESL). One of the biggest issues with such battery-operated electronics is the power consumption. Facilitating power-aware architectural exploration at ESL requires a fast and accurate system-level power analysis capability. Existing frameworks...
Functional validation of System Level Models, such as those modeled with SystemC, is an important and complex problem. One of the problems in their functional validation is the test case generation with good coverage and higher potential to find faults in the design. We propose a coverage-directed test generation framework for system level design validation by combining the synchronous language ESTEREL,...
Given a SystemC IP library, constructing SoC simulation models for design space exploration often distract designers from system architecture concerns to software engineering and programming concerns. Fast design space exploration using a visual architectural specification framework followed by automated IP selection and construction of simulation models without having to programmatically composing...
Composing synchronous intellectual property (IP) blocks over asynchronous communication links for an system-on-chip (SoC) design is a challenging task, especially for ensuring the functional correctness of the overall design. In this paper, we propose a trace based framework to assist in validation of globally asynchronous locally synchronous (GALS) designs. We provide a specific characterization...
Multi threaded graph (MTG) models are expressive in explicitly representing the concurrency, event synchronization, data sharing and timing constraint aspects of a system. Because of their rich expressiveness and visual appeal, MTGs are also useful in conceptualizing these aspects of a system on chip (SoC), before designing them. Each intellectual property block of a system can be captured into an...
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