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A low-power 2Mb ReRAM macro was developed in 90 nm CMOS platform, demonstrating lower power data-writing (x1/7) and faster data-reading (x2∼3) as compared to a conventional flash. The memory window at −6σ for 10 years was confirmed with a high-speed 1-bit ECC considering operating temperature ranging from −40 to 85 °C, where the worst conditions are high-temperature (85°C) “Off” writing and low-temperature...
VT variability degradation induced by negative bias temperature instability (NBTI) and its relation with random dopant fluctuation (RDF) are investigated by a special large-scale (16000 PFETs) device matrix array (DMA) TEG exclusive for NBTI variability measurements. It is clarified that VT variability degradation is suppressed by reducing channel or halo dopant concentration. The suppression mechanism...
The static noise margin (SNM) as well as Vth, gm, body factor, and drain-induced-barrier-lowering (DIBL) in individual transistors in SRAM cells are directly measured by 16k bit device-matrix-array (DMA) SRAM TEG. It is found that, besides Vth variability, DIBL variability degrades SRAM stability and its Vdd dependence while the variability of gm and body factor has only a small effect.
A new normalization method of VT variability in terms of dopant depth profile is developed and applied to measured variation data of MOSFETs with four types of channel dopant (B, Sb, P, As) with different depth profiles. The normalized coefficient shows a constant value indicating the validity of the method. However, it is shown that only B has much larger coefficient, suggesting B has some extra...
Extra VT variability sources in NMOS are investigated using Takeuchi plot. It is clearly shown that VT variation of boron channel NMOS cannot be explained solely by the channel depth profiles. Moreover it is clarified that boron TED is the dominant source of the extra NMOS VT variability. By suppressing the effect of boron TED with backward substrate bias, VT variation of boron channel NMOS comes...
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