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In this chapter we discuss modeling of hardware and translation to VHDL. Translation to SystemC or Verilog is similar. However VHDL is easier to read and we use VHDL synthesis tools. Translation is path complete path from formal models to a circuit. Equally important we need a refinement method to arrive at a formal circuit description that can be translated. This method has some significant differences...
Formal refinement as offered by the B method has been shown to be applicable in practice and to scale up. However, it has been recognised that it is difficult communicate a formal B model with customers. Recently, as an interface to rigorous formal B models the UML has been investigated to facilitate this communication. The UML is generally accepted as being a communicating models of systems. Availability...
The objective of this paper is to present a novel taxonomy of ambient assisted living (AAL) systems that can be used to describe the AAL systems from a data quality perspective. AAL is an active multi-disciplinary research field that has contributed with many solutions to meet the specific needs of the elderly people. Most of these developments involve experts from different domains. A common terminology...
We argue that formal modeling should be the starting point for any serious development of computer systems. This claim poses a challenge for modeling: at first it must cope with the constraints and scale of serious developments. Only then it is a suitable starting point. We present three techniques, refinement, decomposition, and instantiation, that we consider indispensable for modeling large and...
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