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An 8-ns serial access time has been realized in a 4-Mb static RAM with newly proposed circuits (hierarchical shift registers and look-ahead circuits) which can access up to 4 Mb. This memory realizes a 125-MHz fast serial READ/WRITE operation suitable for ultra-high-speed memory systems such as image-processing systems, high-speed testing systems, and supercomputers. This function is also beneficial...
A 20-ns, 4-Mb CMOS SRAM with both 4 M*1 and 1M*4 organizations and fabricated using a quadruple-polysilicon, double-metal, twin-well 0.6- mu m CMOS process technology is described. A word-decoding architecture and a sensitive sense amplifier, combined with an address transition detector (ATD) technique, realize high-speed, low-power operation. Because conventional divided-word-line (DWL) structure...
Two gate arrays, 10k gates with 4.6k bit SRAM and 9k gates with 9.2k bit SRAM, have been developed using 1.5??m rule CMOS technology and two layer metallization. They have realized 1.4ns gate delay (2 input NAND, F/0=3, l=3mm) and 18ns address access time. High testability by scan path technique, RAM data throughput mode and automatic test data generation, and efficient logic design by neat CAD support...
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