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This work presents the mechanism of Stress induced leakage current (SILC) under NBT stress. Experiment results show that there are three kinds of oxide traps generated under NBT stress: hole traps with full recoverable characteristic, hydrogen related traps with irrecoverable characteristic and a kind of positive trap which can promote the hole tunneling after neutralization. The cause of SILC is...
Negative bias temperature instability (NBTI) recovery for pure-SiO2 and plasma-nitrided oxide (PNO)-based PMOSFET has been investigated at room and below temperature. It is found that the generated hole traps in SiON dielectric under NBTI stress has a broadened energy distribution than that in SiO2 dielectric. This broadened maybe due to nitrogen related traps (K center) In SiON. The traps' location...
Negative Bias Temperature Instability (NBTI) is an important reliability problem in deep submicron PMOSFETs. In this paper, we review the recent literature on the possible theoretical foundations and experimental features of NBTI degradation. These features, including temperature activation energy, recovery and SILC under NBTI, actually reflect the different aspect of the same physics mechanism of...
This paper explore the potential of a Metal Insulator Metal gate controlled tunneling Transistor (MIMT) as a high performance device immune to band-to-band tunneling, GIDL, and stochastic channel doping fluctuations. A semi-analytical model was developed and used to guide device optimization. It is shown that the best performance is obtained by increasing the ratio between the permittivity of the...
We derive an HCI degradation model where bond breaking occurs via multiple local excitations as opposed to a classical carrier injection or single-impact excitation assumption. The model predicts a strong Id/W power-law dependence of HCI in addition to typical 1/Vdd dependence and is used to study the impact of conventional and non-conventional scaling on MOSFET HCI degradation versus the main scaling...
This paper describes a biaxial-uniaxial hybridized strained CMOS technology achieved through selective uniaxial relaxation of thick SSOI, dual-stress nitride capping layer, and embedded SiGe source/drain. Through novel strain engineering, nFET/pFET Idsat enhancements as high as 27%/36% have been achieved for sub-40nm devices at 1V with 30% reduction in gate leakage current, while introducing minimum...
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