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Asynchronous controllers based on Asynchronous Finite State Machines (AFSM) are widely used in the control unit design of asynchronous systems. These systems can be implemented in Field Programmable Gate Arrays (FPGAs), which are a low cost design alternative. Different styles have been proposed to implement AFSMs, but all of them have limitations when implemented in FPGAs. Therefore, this paper proposes...
Digital circuit design may demand critical requirements, such as power consumption, robustness, performance, etc., while being implemented in VLSI (Very Large Scale Integration). The asynchronous paradigm presents interesting features that serve as an alternative to these critical requirements. An important class of the asynchronous paradigm is the one called QDI (Quasi Delay Insensitive) circuits...
Asynchronous paradigm is another option for the project of digital systems. Several design styles can be used, where the micropipeline style is the most suitable one for FPGA platforms because it has a simpler control. It is proposed new pipeline architecture to implement asynchronous systems, in bundled-data micropipeline style, having FPGAs as target devices. One drawback of the bundled-data design...
Taking advantage of synchronous and asynchronous paradigms, a new style of design called Globally Synchronous Locally Asynchronous (GSLA) has achieved very interesting results. In this paper, we propose a high-performance interface that allows the communication of synchronous to asynchronous to synchronous modules. Internally, the proposed interface comprises an asynchronous module. The GSLA design...
Mobile devices in industrial settings became commonplace with different handheld equipment and mobile robots using COTS WiFi interfaces for communication. This growth in the use of the wireless medium increases the potential for overload and consequent long delays and high losses. Traffic segregation with different Quality of Service (QoS) classes can attenuate the problem but does not solve it within...
This paper presents a method for an optimized synthesis of asynchronous digital systems having an FPGA as target device. The method employs the decomposition design style (data-path + controller) and uses the extended burst-mode specification to describe the controller. Asynchronous system synthesized by the method operates in “two-phase handshake protocol”, allowing a better performance. In this...
The asynchronous paradigm has interesting features due to the lack of the clock signal and it is another option for the project of digital systems. This paradigm has several design styles, where the micropipeline style is the most suitable one for FPGA platforms, due to the simplicity of its control. In this paper, we propose a pipeline architecture to implement asynchronous digital systems, in bundled-data...
Complex synchronous digital systems can be implemented on FPGAs (Field Programmable Gate Arrays), but due to the global clock, might have problems with clock skew, performance degradation and increased of power consumed. An alternative to these designs is the asynchronous paradigm that solves the problems related to the clock. However it is difficult to design asynchronous circuits, especially in...
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