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This paper presents a low-power decision-feedback equalizer (DFE) receiver front-end and a two-step minimum bit-error-rate (BER) adaptation algorithm. A high energy efficiency of 0.46 mW/Gbps is made possible by the combination of a direct-feedback finite-impulse-response (FIR) DFE, an infinite-impulse-response (IIR) DFE, and a clock-and-data recovery (CDR) circuit with adjustable timing offsets....
An all-digital DLL with 2-cycle lock time and 47-mUIpp jitter without dithering is presented. Implemented in 65nm CMOS, the DLL consumes only 1.3-mW at 1.6-GHz and occupies 0.016-mm2, making it suitable for low-cost clock deskewing and data alignment circuits in large-scale 3D ICs. A set of custom-designed, serially-connected control registers whose propagation delay is matched to that of the delay...
A 1 Gb density, 5.2 Gbps/s/pin data rate GDDR5 SDRAM was developed using 66 nm DRAM process. It uses traditional Core architecture, 8-bit pre-fetch with 16-banks, but the clocking and interface topology are fully changed for operating more than 4 Gbps without using differential signaling. Major barrier to achieving high data bandwidth is the clock jitter. To overcome this limitation, this project...
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