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In this paper, we present a new beacon recognition method for wireless sensor devices to access beacon-enabled WSN with low-power consumption. At first, we explain necessity of the low-power beacon recognition in the beacon-enabled wireless sensor networks. By realigning network resources, we catch that beacons are in the same position in each BI (beacon interval). Then, we propose how to switch operation...
This paper presents a CMOS third order ΔΣ modulator with inverter-based integrators for low power audio signal processing application. In order to minimize the power consumption of the proposed modulator, the inverters embedded into integrators and an analog adder operating in the subthreshold region were implemented on an 180nm CMOS technology with digital and analog power supply of 1.8V and 0.8V,...
The emergence of IoT (Internet of Things) has brought various studies on low-power techniques back to embedded systems. In general, minimizing power consumed by program executions is the main consideration of system design. While running programs, executing data-dependent program code results in a large number of memory accesses which consume huge amount of power. Further, most embedded systems consist...
A single-channel 10b pipelined SAR ADC with a gm-cell residue amplifier and a current-mode fine SAR ADC achieves a 500MS/s conversion rate in a 28nm CMOS process under a 1.0 V supply. With background offset and gain calibration, the prototype ADC achieves an SNDR of 56.6dB at Nyquist. With power consumption of 6mW, it obtains a FoM of 21.7fJ/conversion-step.
Recently, face recognition (FR) based on always-on CIS has been investigated for the next-generation UI/UX of wearable devices. A FR system, shown in Fig. 14.6.1, was developed as a life-cycle analyzer or a personal black box, constantly recording the people we meet, along with time and place information. In addition, FR with always-on capability can be used for user authentication for secure access...
Wearable devices such as smart watches become popular, especially thanks to connectivity with smartphones. They are, however, sensitive to energy consumption that is caused by computation and networking capabilities. This motivates to develop task offloading techniques that enable to perform task computation on smartphones rather than on wearable devices. In this paper, we propose a new offloading...
We demonstrate a low-power wireline transmitter with 2-tap pre-emphasis in which serialization is achieved by toggling serializer with data transition information extracted from parallel input data. This novel technique of serialization provides significantly reduced power consumption since it does not need the short pulse generation block required in the conventional serializer. In addition, the...
Energy-efficient design approaches for always-on imaging will be reviewed. Circuit design techniques including dynamic voltage scaling (DVS), dynamic current scaling (DCS), and dynamic frequency scaling (DFS) will be described. In addition, energy-efficient architecture for image signal readout will be described. Finally, power reduction techniques by adaptively suppressing spatial and temporal bandwidth...
In deep sub-micron technology, leakage power consumption has become a major concern in VLSI circuits, especially for SRAM, which is used to build the cache in System-on-Chip (SOC). In this paper, a low power 8-T SRAM cell, based on carbon nanotube field effect transistor (CNFET), is proposed to circumvent the leakage power issue. Experiment datas show that the proposed SRAM cell can save 97.94% static...
A new type of multi-rate clock and data recovery (CDR) circuit is realized that can operate at multiple data rates of 3.5, 7.0 and 14-Gb/s. A multi-mode rotational binary phase detector supports full-rate, half-rate and quarter-rate CDR operation with only one voltage-controlled oscillator. A prototype CDR circuit implemented in 65nm CMOS technology successfully demonstrates the multi-rate operation...
A 10b LCD column driver with resistor-resistor string DAC (RRDAC) is proposed having 0.24, 0.37 LSB of DNL and INL, and 17.4% of area shrinkage compared with an 8b LCD column driver with traditional resistor string DACs. To resolve the problems of the previous RRDACs such as power consumption increase, and inapplicability for nonlinear gamma curve, we propose an RRDAC using voltage-drop compensated...
A low-power counter (LPC) for column-parallel CMOS image sensors (CISs) is presented. The proposed LPCs can reduce the number of switching events of D-flip-flop (DFF) in the counter by 50% compared to the traditional counter. The simulation results with 200 MHz of clock signal show that the power consumption of the traditional counter is 55.7 μW, and the proposed LPC is 27.9 μW.
As deep neural networks grow larger, they suffer from a huge number of weights, and thus reducing the overhead of handling those weights becomes one of key challenges nowadays. This paper presents a new approach to binarizing neural networks, where the weights are pruned and forced to take degenerate binary values. Experimental results show that the proposed approach achieves significant reductions...
Many people around the world are adversely affected by various unforeseen disasters such as earthquakes, fires, and acts of terror. To resolve these problems, Kansai University has proposed the Emergency Rescue Evacuation Support System (ERESS). We propose a novel isopleth-oriented multi-hop communication method using clustering control to reduce the amount of data traffic by allowing only parent...
The depth information is actively utilized for many applications such as mobile gesture user interface (UI). However, the previous stereo vision systems are unsuitable for the mobile gesture UI due to the long latency and the high-power consumption of external image sensor in embedded environments. In this paper, we propose a CMOS image sensor-based real-time stereo matching accelerator with low power...
Power transfer efficiency of wireless power transfer (WPT) system is a primary concern to design and develop the WPT system. However, the power consumption in standby mode is rarely researched and reported in the literature. Since a number of WPT system rapidly increases, it is necessary to develop a standby power reduction technique for WPT system. This paper proposes a standby power reduction method...
Wearable head-mounted display (HMD) smart devices are emerging as a smartphone substitute due to their ease of use and suitability for advanced applications, such as gaming and augmented reality (AR) [1–2]. Most current HMD systems suffer from: 1) a lack of rich user interfaces, 2) short battery life, and 3) heavy weight. Although current HMDs (e.g. Google Glass) use a touch panel and voice commands...
Miniaturized computing platforms typically operate under restricted battery capacity due to their size [1]. Due to low duty cycles in many sensing applications, sleep-mode power can dominate the total energy budget. Wakeup timers are a key always-on component in such sleep modes and must therefore be designed with aggressive power consumption targets (e.g., <10nW). Also, accurate timing generation...
In this paper, we propose a supply and demand management system based on information on the power consumption pattern analysis and the tariff for HEMS(Home Energy Management System) of KEPCO(Korea Electric Power COrporation) for cost minimization. The scheduler of a supply and demand management system decides the curtailment level for the dropped appliances based on information about the predicted...
As the numbers of ICT assets consumers own are increasing, consumers have problems managing and maintaining their personal ICT assets. Consumers are used to unnecessary consumption because they cannot predict the lifetime of ICT assets. Also, consumers sometimes throw away old electronic devices including sensitive personal information. To solve these problems, the personal ICT Asset management service...
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