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Finite Element simulations are often used to study the reliability of solder joints subjected to thermal cycling. Packaging configurations are becoming more complex to accommodate better functionality and performance. Increased complexity leads to several challenges for FE models including difficulties modeling thin layers and interfaces, as well as keeping the total numbers of nodes and elements...
The assessment of board level solder joint reliability during thermal cycling is very important for electronic packages. During thermal cycling, the mismatch in Coefficient of Thermal Expansion (CTE) between the materials used in the package induces stress on the solder interconnects and results in deformation and stresses. Finite element tools are widely used for rapid design optimization and also...
The reliability life assessment of electronic packages is a key issue to ensure the mass production quality of packaging components. To meet the time-to-market and long term reliability requirements, using finite element to predict a precise life cycle of solder joints becomes the main trend of electronic packaging product development. Thermal cycling test is a standard test and has been widely used...
Finite element model (FEM) simulations have been performed to elucidate the effect of flat plate photovoltaic (PV) module materials and design on PbSn eutectic solder joint thermal fatigue durability. The statistical method of Latin Hypercube sampling was employed to investigate the sensitivity of simulated damage to each input variable. Variables of laminate material properties and their thicknesses...
In the electronic industry the portable devices are becoming the prime factors to dominate the market share. And with the blessing of miniaturization, these devices are also becoming smaller and smaller day by day. On the other hand, with this miniaturization process these devices are becoming more susceptible to drop impact loading. To ensure product quality and to integrate more complicated functionality...
Whether low or high temperature brazing seal structure, the solder joint shapes are important concern for the residual stress distributions. Many investigations of the residual stress distributions with the ideal solder joint shape in the brazing seal so far have been carried out theoretically and experimentally, whereas ones of the residual stress distributions with actual solder joint shape in these...
In this study, the drop test simulation for a typical stacked memory device with 8 units integrated vertically on board-level was performed by finite element method. The units were connected with each other through copper lead frames and assembled on the PCB by pins. The computational model of the device was built in ANSYS and the drop test of this board-level assembled device was investigated by...
In this study, the drop test simulation for a typical stacked memory device with 8 units integrated vertically on board-level was performed by finite element method. The units were connected with each other through copper lead frames and assembled on the PCB by pins. The computational model of the device was built in ANSYS and the drop test of this board-level assembled device was investigated by...
One of the most critical failure modes in a BGA package is the solder interconnect failure (2nd level). Conventionally, the solder damage is due to the mismatch of coefficient of thermal expansion (CTE) between the various package components and the PCB. It is absolutely critical to identify and minimize the BGA damage under thermal cycling to improve the package reliability. In the past, the critical...
The dropping test of WLCSP with RDL on board-level was investigated by numerical method in this study. The asymmetric pattern of WLCSP devices mounted on the PCB board was considered. Using the finite element analysis, the stress and energy in the WLCSP with RDL was predicted under the dropping test conditions. The critical locations of WLCSP device on the PCB in the dropping test were identified...
In this paper, the fine pitch ball grid array (FBGA) assembly with lead free solder was tested under thermal cycling condition. Finite element modeling and simulation was conducted. The microstructure designs of via in pad of substrate and through hole (via) in PCB under the solder joint were simulated. The solder mask definition (SMD) and non-solder mask definition (NSMD) on PCB board side was also...
The solder joint fatigue life of flip chips and ball grid array packages has been extensively studied and published. However, there are only a few published papers available on the solder joint reliability of a non-leaded, surface mounted package such as the MLPQ (Micro Leadframe Quad Package). In this paper, a non linear Darveaux's solder joint fatigue model has been used to predict the fatigue life...
LGA sockets are becoming the leading technology to connect the micro-processors with the system boards of desktop or server computers. It is critical to understand the mechanical behavior of a socket to predict its required enabling load and reliability to certain confidence at the design phase. FEA has been used to achieve this goal at both component and system levels. This paper presents a sensitivity...
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