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Low power and robust circuitry are permanent hots pots in VLSI design. Adiabatic logic is one of potential breakthroughs for these goals. Especially, designing reliable clock tree is very significant for adiabatic logic due to four-phase clocked power required for pipelined data transmission in adiabatic system. In this paper, we present analysis of charging speed and clock types that influence power...
Data with increasing bandwidth requires future general-purpose as well as application specific microprocessors to improve performance endlessly. Transistor scaling, novel transistor structures, novel state-of-art VLSI design techniques and new computer architectures are the key drivers for boosting power and performance of microprocessors. Unfortunately, the processor cooling technique is unable to...
The lack of well defined abstraction levels and immature design tools have made the custom design and optimization of analog circuits slow, complex and laborious. Furthermore, CMOS technology beyond 10 nm faces fundamental limits which may restrict its applicability for future devices. In this paper, a Graphene Field Effect Transistor (GFET) based cross-coupled LC circuit is used as case study to...
Achieving lightning fast speed data communication in Chip Multi Processor (CMP) based systems as well as Networkon Chips (NoCs) is always desired for target performance. Data communication links inside the communication fabric of CMP or NoC architectures have strong impact on their performance and power dissipation. Several approaches exist to reduce power dissipation of parallel link on-chip interconnects,...
Graphene which is a single atom layer of carbon film with the interesting properties of high carrier mobility, high carrier concentration, high thermal conductivity, high velocity saturation, and reduced short channel effects, is emerging as a replacement of the ubiquitous silicon. This is particularly true for high-speed analog and radio-frequency electronics due to low Ion/Ioff ratio. In this paper,...
The Illinois Scan Architecture (ILS) consists of several scan path segments and is useful in reducing test application time and test data volume for high density chips. In this paper, we propose a scheme of layout-aware as well as coverage-driven ILS design. The partitioning of the flip-flops into ILS segments is determined by their geometric locations, whereas the set of the flip-flops to be placed...
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on a chip (SoC) technology. Hence, simultaneous or parallel read/write (R/W) access multi-port SRAM bitcells are widely employed in such embedded systems. In this paper, we present a 2-port 6T SRAM bitcell with multi-port capabilities...
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