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In this paper, we propose two different hardware structure of SHA-3 hash algorithm for different width of circuit interface. They both support the four functions SHA3-224/256/384/512 of SHA-3 algorithm. The padding unit of our design is also implemented by hardware instead of software. Besides, a 3-round-in-1 structure is proposed to speed up the throughput of our circuit. We conduct an implementation...
In this work, we propose a novel basic element called delay chain feedback loop (DCFL) to generate metastability. Using 16 DCFLs with different delay chains, a new digital true random number generator (TRNG) is constructed. The new TRNG has been implemented on Altera Cyclone II and Altera Cyclone IV FPGAs. The experimental results show that the TRNG is true random which can pass both the NIST and...
In this paper the authors evaluated bus buffer size of different arbitration algorithms according to a RISC microprocessor. Three arbitration algorithms have been tested: (a) static priority arbitration; (b) rotating priority arbitration; and (c) lottery bus arbitration. A high-level simulation model based on C++ has been developed and the simulations were based upon recorded real communication traces...
Inserting bus buffer is one significant method for solving the collisions in the microprocessor. And it is pivotal to determine the buffer size because of the performance and hardware resource constraints. This paper proposes a method for estimating the buffer size based on a prioritized M/G/1 queuing model and a high-level simulation model according to a RISC microprocessor. Both the results of queuing...
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