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In this paper, a new ultra-thin body and BOX (UT2B) fully-depleted (FD) silicon-on-insulator (SOI) device architecture based on a stacked back plane (BP) and WELL below the BOX is presented. The proposed device has been developed to boost the gate-to-channel electrostatic control and to be compatible with the adaptive body biasing (ABB) techniques for low power applications. The concept viability...
In this paper, an original and simple concept for setting up multi-VT for fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs is presented. Low, standard and high threshold voltage (VT) devices are achieved without degrading the good channel electrostatic control and the low VT dispersion of the FDSOI technology. The concept is based on the use of a thin buried oxide (BOx) combined with the integration...
Tri-gate FinFlash devices are one of the most promising solutions to solve scaling problems of Flash memories. The use of Silicon Nanocrystal storage nodes in novel 3D FinFET architecture offers the possibility of scaled gate dielectrics (implying scaled operating voltages), along with short channel effect immunity and higher sensing current drivability. In this paper, we investigate the channel length...
This work presents TCAD simulations of NOR NC memories performed with commercial tools, which allow for a good understanding of the impact of the localized charge on both electrostatics and dynamics of the cell. The key role of the position of the trapped charges along the channel length on the threshold voltage shift has been put in evidence. Indeed, this result is critical for NOR discrete-trap...
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