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We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground...
In this paper, a new ultra-thin body and BOX (UT2B) fully-depleted (FD) silicon-on-insulator (SOI) device architecture based on a stacked back plane (BP) and WELL below the BOX is presented. The proposed device has been developed to boost the gate-to-channel electrostatic control and to be compatible with the adaptive body biasing (ABB) techniques for low power applications. The concept viability...
Recent device developments and achievements have shown that undoped channel planar Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 22nm node and below. This planar option seems to be even easier than non planar FinFET devices. This paper will report the main results obtained with this technology and will compare these results with the state of the art of Bulk...
Sources responsible for local and inter-die threshold voltage (Vt) variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack are experimentally discriminated for the first time. Charges in the gate dielectric and/or TiN gate workfunction fluctuations are determined as major contributors to the local Vt variability and it is found that SOI thickness (TSi) variations have a negligible...
We demonstrate for the first time 70 nm gate length TiN/HfO2 pMOSFETs on 200 mm GeOI wafers, with excellent performances: ION=330 muA/mum & IOFF=1 muA/mum @ Vd=-1.2 V (without germanide). These performances are obtained using adapted counterdoping and pocket implants. We report the best CV/I vs. IOFF trade-off for Ge or GeOI: CV/I=4.4 ps, IOFF=500 nA/mum @ Vd=-1 V. Moreover, based on fine electrical...
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