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In this paper, a PVT Insensitive Time to Digital Converter is proposed to provide a stable reference clock signal of a phase-locked loop. The time resolution can be independent on process, voltage, and temperature variations. In order to produce 16-phase signals, eight series of differential delay elements are utilized. Then, interpolated architecture is used to increase the reference frequency such...
Deep sub-wavelength lithography, i.e., using the 193 nm lithography to print 45 nm, 32 nm, and possibly 22 nm integrated circuits, is one of the most fundamental limitations for the continuous CMOS scaling. Lithography printability is strongly layout dependent, thus routing plays an important role in addressing the overall circuit manufacturability and product yield since it is the last major physical...
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