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The jitter and the phase noise of ring oscillators utilizing subthreshold source-coupled logic (STSCL) style are analyzed in this paper. Closed-form equations are derived to predict the jitter and phase noise caused by white and flicker noise. Measurement results of a test chip fabricated in a standard CMOS 90 nm technology are presented to validate these expressions. The performed analysis shows...
Physically unclonable functions (PUFs) enable information security down to the chip level [1-4]. Arrays of PUF bitcells (Fig. 14.3.1) generate chip-specific keys that are unpredictable, repeatable and cannot be measured externally, thus uniquely identifying the die to counteract chip piracy/counterfeiting and enable lightweight authentication/encryption [1-4]. In silicon PUFs, trustworthy bit generation...
In this paper, a simple topology to reduce delay variations in domino logic gates is discussed. According to a previous analysis by the same authors, the feedback loop implemented by the keeper transistor and the output inverter gate is responsible for a delay variability increase, compared to static CMOS logic. The proposed strategy reduces the loop gain associated with this feedback loop, and hence...
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