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In this paper, a variation-aware simulation framework is introduced for hybrid circuits comprising MOS transistors and spintronic devices (e.g., magnetic tunnel junction-MTJ). The simulation framework is based on one-time characterization via micromagnetic multi-domain simulations, as opposed to most of existing frameworks based on single-domain analysis. As further distinctive capability, stochastic...
Clock network optimization is substantially affected by the operating voltage VDD, as the clock skew is dominated by different mechanisms and has a different balance between wire and repeater delay at different VDD (Fig. 26.3.1). At above-threshold VDD, deep clock networks with several levels of repeaters are needed to control the clock slope in wires [1]. At sub-threshold VDD, shallow networks are...
It is well known that technology scaling has led to increasing process/voltage/temperature/aging margins that substantially degrade performance and power in modern processors and SoCs. One approach to address these large timing margins is the use of specialized registers on critical paths that perform error detection and correction (EDAC) [1-5]. While promising, the previously proposed implementations...
In this paper, the impact of variations on the most representative pulsed flip-flops topologies is comparatively evaluated in 65-nm CMOS. The analysis explicitly considers fundamental sources of variations such as process, voltage, temperature and clock slope. For each FF topology, the variations are statistically evaluated through Monte Carlo simulations and they explicitly include the non-negligible...
Lightweight encryption circuits are crucial to ensure adequate information security in emerging millimeter-scale platforms for the Internet of Things, which are required to deliver moderately high throughput under stringent area and energy budgets. This requires the adoption of specialized AES accelerators, as they offer orders of magnitude energy improvements over microcontroller-based implementations...
This paper investigates the impact of voltage scaling on the energy and the performance of STT-RAM bitcells during write operation. Analytical models of energy scaling and performance degradation are derived to gain an insight into the energy-performance tradeoff at low voltages. Minimum-energy operation is explored through optimization of the supply voltage, with energy savings in the order of 20%...
The jitter and the phase noise of ring oscillators utilizing subthreshold source-coupled logic (STSCL) style are analyzed in this paper. Closed-form equations are derived to predict the jitter and phase noise caused by white and flicker noise. Measurement results of a test chip fabricated in a standard CMOS 90 nm technology are presented to validate these expressions. The performed analysis shows...
In this paper, the impact of variations on the most representative double-edge triggered flip-flop (FF) topologies is comparatively evaluated in 65-nm CMOS. The analysis explicitly considers fundamental sources of variations such as process, voltage and temperature (PVT) variations. For each FF topology, the variations of the performance, the energy per cycle and the leakage power are statistically...
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