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In this paper, a simple topology to reduce delay variations in domino logic gates is discussed. According to a previous analysis by the same authors, the feedback loop implemented by the keeper transistor and the output inverter gate is responsible for a delay variability increase, compared to static CMOS logic. The proposed strategy reduces the loop gain associated with this feedback loop, and hence...
Flip-flops (FFs) are key building blocks in the design of high-speed energy-efficient microprocessors, as their data-to-output delay (D-Q) and power dissipation strongly affect the processor's clock period and overall power [1]. From previous analyses [2], the Transmission-Gate Pulsed Latch (TGPL) [3] proved to be the most energy-efficient FF in a large portion of the design space, ranging from high...
In this paper, the tapered-VTH methodology to design energy-efficient buffers in deep nanometer CMOS technology is deeply analyzed. Its effectiveness is demonstrated under various working conditions (variable final load, activity factor, supply voltage and process corner). Simulations based on a 45-nm technology showed that the tapered-VTH approach can provide a 3X energy reduction, at the parity...
This study aims to understand the potential of buried Silicon-Germanium (SiGe) technology from the perspective of VLSI logic circuits exploiting aggressive dynamic voltage scaling. Appropriate circuit- and system-level metrics are extracted from wafer-level measurements on 45nm SiGe pMOSFETs with a high-k/metal gate stack and systematically benchmarked to Si channel devices. The comparative analysis...
In this paper, a comparison of representative Dual-Edge-Triggered flip-flop topologies is carried out in a 65-nm CMOS technology. The energy efficiency is analyzed together with other aspects, such as the area-delay tradeoff, leakage and clock-load, which are typically neglected in previous works. The investigation highlights the impact of effects that become dominant in nanometer technologies (e...
In this paper, the novel “tapered-Vth” approach to design energy-efficient CMOS buffers is introduced. In this approach, the substantial energy consumption due to leakage is reduced by tapering the threshold voltage throughout the buffer stages, other than tapering the transistor size. More specifically, the threshold voltage is progressively reduced when going from the last to the first stage. This...
In this paper, a novel technique to reduce the leakage current under an assigned delay constraint is presented for FinFET forced stacks. This technique is based on the adoption of different back bias voltages in stacked four-terminal (4T) FinFETs (as is well known, this would not be possible in bulk CMOS circuits). In particular, a Reverse Back Bias (RBB) voltage is applied to one of the two stacked...
A comprehensive design flow, easy to automate with commercial CAD tools, is presented to optimize nanometer FFs under constraints within the E-D space. By referring to practical design cases, transistor sizing is addressed rigorously. Cases of study for FFs in a 65-nm technology are reported for validation.
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