The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Si-tunneling field effect transistors (TFETs) with a record Ion >100 μA/μm and high Ion/Ioff ratio (> 105) at Vds=1V are reported. Using an optimal spike and millisec flash anneal coupled with an engineered source-gate overlap through a gate-last process, Si TFETs have been demonstrated with 10 to 1000 times greater current than previously reported. The devices exhibit negative differential...
We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation. It produces steep subthreshold swing (SS) of 46 mV/dec and high ION/IOFF ratio (~108) and the experiment was successfully repeated after two months. Its superior operation is explained...
A method to characterize distributions of read and write margins of an SRAM array using tunable ring oscillators (ROs) is presented. A 45nm CMOS testchip demonstrates a write RO with frequency that correlates well with static wordline write-trip voltage and a read RO that that correlates well with the static-current noise margin as well as with the cell read current.
An alternating-bias random telegraph signal (RTS) characterization technique is presented, which shortens measurement time by 10?? and also produces more accurate statistical distributions of RTS amplitudes. Measurements of RTS amplitudes in 45 nm SRAM transistor Ids and cell write margin are reported and used to demonstrate a complex dependence of write margin on RTS in multiple transistors. Fail...
Increased process variability presents a major challenge for future SRAM scaling. Fast and accurate validation of SRAM read stability and writeability margins is crucial for estimating yield in large SRAM arrays. Conventional SRAM read/write metrics are characterized through test structures that are able to provide limited hardware measurement data and cannot be used to investigate cell bit fails...
Distributions of read and write noise margins in large CMOS SRAM arrays are investigated by directly measuring the bit-line current during bitline / wordline (write) or cell supply (read) voltage sweep in a 768 Kb 45 nm CMOS SRAM test-chip. Good correlation between write/read margin estimates through the bit-line measurements and the DC read SNM (RSNM) and IW measurements in small on-chip SRAM macros...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.