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This paper presents a low-cost technique to reduce offset voltage of a dynamic comparator. The proposed method is based on output-data phase measuring. A full-digital implementation is used to measure phase without impacting offset accuracy. Simulation and measured results show that the eye-diagram at the compartor input can be shifted up to 245mV due to offset, achieving a successful correction,...
This paper presents an alternative to prevent data corruption in DRAM memories due to Row Hammer attacks. The proposal is based on the usage of dummy cells connected to each row as attacks indicator. These special cells are characterized for having a higher sensitivity to coupling noise. The strategy was validated by simulations on a 65nm CMOS 64×64 memory array, including process variations for coupling...
This paper describes a low-cost and low-complexity alternative to reduce the occurrence of Row-Hammer attacks. The detection of an undesired attack is based on the use of an additional memory cell — called dummy cell —, with a larger leakage current and thus a higher sensitivity to crosstalk and coupling noise. This characteristic is achieved due to the use of a wider pass transistor and a smaller...
This paper presents an offset voltage correction technique for high-speed digital interfaces. Contrary to conventional way of measuring offset, the proposed technique is based on the phase measurement of a slicer output avoiding the input connection to a common mode voltage. A fully-digital implementation allows phase measurement maintaining offset accuracy. Proper operation of calibration technique...
This paper presents a technique to reduce offset voltage of a dynamic comparator. Contrary to conventional way of measuring offset, the proposed technique is based on phase measurement of comparator output. A full-digital implementation is used to measure phase without impacting offset accuracy. Simulation results show a reduction of more than ten times in the comparator offset with a small increment...
In this paper the design of a very low-voltage current mirror with an enhanced output resistance is presented. The mirror is designed using transistors in weak-inversion region, which allows operating with reduced supply voltage. With the use of multiple feedback loops, parameters such as minimum output voltage and output resistance are kept constant with respect to supply voltage, temperature and...
In this paper the design of a robust to Process, Voltage and Temperature (PVT) variations fully-differential voltage amplifier is presented. The proposed circuit is implemented in a standard digital CMOS technology as 45 nm–1 V Silicon-on-Insulator. The robustness of the circuit is achieved through the use of a novel input stage, which combines two single-ended differential pairs to obtain a fully-differential...
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