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This paper demonstrates bit-parallel, all-to-all communication with AWGR for on-board optical interconnects. A flexible bandwidth allocation is also presented. Trade-off studies optimize the bit-parallelism and achieve up to 3.5× higher energy efficiency compared to the single-bit case.
In future performance improvement of the basic building block of supercomputers has to come through increased integration enabled by 3D (vertical) and 2.5D (horizontal) die-stacking. But to take advantage of this integration we need an interconnection network between the memory and compute die that not only can provide an order of magnitude higher bandwidth but also consume an order of magnitude less...
This paper presents flexible bandwidth solutions for Datacom optical networks exploiting AWGR technology, DVFS and channel bonding techniques. Benchmarking simulations and experiments demonstrate up to 2× reduction in energy consumption and 1.77× throughput increase.
This study presents simulation studies on the execution time and energy consumption of optical multi-socket boards with on-chip, all-to-all, and contention-less arrayed waveguide grating routers-based interconnection. This study considers throughput and energy-efficiency optimizations based on dynamic voltage and frequency scaling under realistic, shared memory, and cache-coherent PARSEC benchmarking...
We propose a scalable multi-board HPC blade architecture with optical interconnection based on wavelength routing in Arrayed Waveguide Grating Routers (AWGRs). Benchmarking simulations show reductions up to 2× in energy consumption and 3× in execution time.
We analyze the execution time and energy performance of tiled optical multi-socket HPC boards with all-to-all AWGR-based interconnection and with different optimizations techniques under PARSEC benchmarking traffic, and we compare it with a state-of-the-art electronic multi-socket architecture. Benchmark results show significant performance improvements and up to 2× energy saving when using dynamic...
Speed-up in computing systems today is most often accomplished by increasing parallelism in both hardware and software. Parallel applications residing wholly on a single multi-core chip generally utilize implicit inter-thread communication via shared memory managed by cache-coherency mechanisms. However, increasing parallelism by creating coherent domains across many chips poses new challenges. In...
Nanophotonic is a promising solution for interconnections in future chip multiprocessors (CMPs) due to its intrinsic low-latency and low-power features. This paper proposes an integrated approach with physical level design choices to select the most suitable optical network topology, and an adhoc software strategy to improve performance and reduce energy consumption of a tiled CMP architecture. We...
Many crossbenchmarking results reported in the open literature provide optimistic expectations on the use of optical networks-on-chip (ONoCs) for high-performance and low-power on-chip communication in future manycore systems. The goal of this paper is to highlight key methodological steps for a realistic assessment of the emerging nanophotonic technology. Building on this methodology, the paper provides...
This paper proposes a tiled chip multiprocessor (CMP) architecture built around an all-optical reconfigurable network, thought to significantly reduce path-setup latency and energy consumption. We propose a novel optical path-setup procedure that is able to configure multiple optical switches simultaneously. Our architecture uses a simple ring-based path-setup network for assisting an optical folded...
This abstract wants to be an excursus on the different solutions in which an optical Network-on-Chip (NoC) could be applied to, starting from passive NoC topologies (Mesh/Torus) enhanced by a simple shared optical ring and moving to more complex all-optical reconfigurable networks, in a state-of-the-art coherence assisted Chip-Multi-Processor (CMP). We investigate performance and power consumption...
Many crossbenchmarking results reported in the open literature raise optimistic expectations on the use of optical networks-on-chip (ONoCs) for high-performance and low-power on-chip communication. However, most of those previous works ultimately fail to make a compelling case for chip-level nanopho-tonic NoCs, especially for the lack of aggressive electronic baselines (ENoC), and the poor accuracy...
Nanophotonic interconnection is a promising solution for inter-core communication in future chip multiprocessors (CMPs). Main benefits derive from its intrinsic low-latency and high-bandwidth, especially when employing wavelength division multiplexing (WDM), as well as reduced power requirements when compared to electronic NoCs. Existing works on optical NoCs (ONoC) mainly concentrate on relatively...
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