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Recent years have seen a growth in the use of algorithmic techniques, and especially formal methods, in reverse engineering. Depending on the motivation and requirements of the attacker, algorithms can be used for reconstructing circuit netlists, extracting a higher-level description of a circuit from unstructured sea-of-gates, or resynthesizing the Boolean function of a logic circuit from examples...
Advances in reverse engineering make it challenging to deploy any on-chip information in a way that is hidden from a determined attacker. A variety of techniques have been proposed for design obfuscation including look-alike cells in which functionality is determined by hard to observe mechanisms including dummy vias or transistor threshold voltages. Threshold-based obfuscation is especially promising...
Approximate computing has recently emerged as a promising method to meet the low power requirements of digital designs. The erroneous outputs produced in approximate computing can be partially a function of each chip's process variation. We show that, in such schemes, the erroneous outputs produced on each chip instance can reveal the identity of the chip that performed the computation, possibly jeopardizing...
Gate camouflaging is a technique for obfuscating the function of a circuit against reverse engineering attacks. However, if an adversary has pre-existing knowledge about the set of functions that are viable for an application, random camouflaging of gates will not obfuscate the function well. In this case, the adversary can target their search, and only needs to decide whether each of the viable functions...
Numerous side-channel attacks on integrated circuitimplementations of cryptographic systems have been demonstrated in literature. Insecure implementations can reveal secret information through data dependencies in dynamic and leakage power profiles. Side-channel resistant logic styles are effective against dynamic power analysis attacks, but are suggested to exhibit weaknesses against the less common...
Technology scaling, increasing transistor density, and design complexity poses new challenges in testing of digital systems. IJTAG is a new proposed standard to access embedded instruments in a chip. However, with growing complexity of embedded chips, shifting data serially might result in high test application time. In this paper, a preemptive parallel test scheduling method for IJTAG environment...
Multigigahertz range of working frequency, shrinking of technology and loss of signal integrity put circuits' interconnection at a higher risk of permanent or more frequent transient faults. These faults reduce overall reliability and performance of the circuit. Because of this, testing interconnects becomes an important issue. This paper presents an offline interconnect testing method that improves...
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