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A novel Bidirectional Fault-Tolerant NoC (BFT-NoC) architecture capable of mitigating both static and dynamic channel failures is proposed. In a traditional NoC platform, a faulty data channel will force blocked packets to make costly detours, resulting in significant performance hits. In this work, novel fault-tolerance measures for a bidirectional NoC platform are proposed. The dynamically reconfigurable...
A novel Turn-Model based Fully-Adaptive-Routing (TM-FAR) algorithm is proposed for Networks-on-Chip (NoC). TM-FAR retains the deadlock-free property of traditional turn-model based routing algorithms (e.g., XY, Odd-Even), while alleviating restrictions on turn and path selections. Just like the current Virtual-Channel based Fully-Adaptive-Routing (VC-FAR) algorithm, TM-FAR allows full exploitation...
A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. The BiNoC allows each communication channel to be dynamically self-configured to transmit flits in either direction in order to better utilize on-chip hardware resources. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher...
Today's process technologies place emphasis on low power design in multi-core systems that require the complicate communication networks-on-chip (NoC) architecture to be reliable. Considering the many error control codes (ECCs) implemented in a hardware NoC router, the primary objective of this paper is accounting for the causes of energy consumed for fault tolerance and providing a way of comparison...
In this paper, we utilize a novel fluidity concept to analyze and develop routing algorithms in network-on-chip for congestion avoidance and relief. We develop a new model to capture congestion information which improves the performance of routing algorithms. Comparisons of algorithms using our model consistently outperform the original algorithms themselves.
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