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A coupled-electro-thermal RDS(ON) (drain to source ON resistance) co-analysis methodology for Power MOSFET is proposed. The methodology contains two functional modules: 1) physical field solvers and 2) equivalent circuit/network solver. The field solver resolves the electrical and thermal field variables by the conventional 3D finite-element method, while the network solver can achieve accurate and...
In this paper we detail the silicon-package electrical co-design of a 45nm CMOS, 400MHz to 4GHz, 3GPP TDD & FDD, RF-to-Serdes base station transceiver system on chip (SoC). Electrical optimization of the silicon-package RF paths, to achieve desired performance, was achieved through a coupled circuit-to-electromagnetic co-design modeling and simulation flow. Laboratory measurements, on a real SoC...
Multiplexer/switch ICs are key components of NVDIMM architecture that serve to isolate the host controller from the DRAM memory system. Signal integrity performance of the IC can drastically be impacted by package parasitics. In this paper we detailed a system co-design methodology that was employed to design a cost-effective DDR4 switch packaged in a laminate-based chip-scale packaging (CSP), without...
The process of troubleshooting a 12.5Gbps SFF-8431 channel return loss compliance failure is described in details. Excellent simulation to measurement correlation has been achieved after capturing a capacitive dip at the package/PCB interface (“phantom” capacitance) with package and board physical layout geometries merged into one single electromagnetic simulation. Source of the “phantom” capacitance...
In this paper we described a PCB system co-design modeling methodology that can be implemented, early in the system design phase, to improve system-level immunity performance in the presence of IEC electromagnetic transient disturbances. The methodology is validated through correlation to laboratory measurements on a TI MSP430™ microcontroller PCB system.
Skinny trace compensation is a simple yet effective technique for overcoming capacitive impedance discontinuities on high speed channels. This paper provides a comprehensive system-level modeling and analysis methodology for implementing this technique on high speed serial interface. System level simulation correlation to laboratory measurement for the HDMI (High Definition Multimedia Interface) interface...
As System-on-Chip (SoC) designs migrate to 28nm process node and beyond, the electromagnetic (EM) co-interactions of the Chip-Package-Printed Circuit Board (PCB) becomes critical and require accurate and efficient characterization and verification. In this paper a fast, scalable, and parallelized boundary element based integral EM solutions to Maxwell equations is presented. The accuracy of the full-wave...
Package and PCB‐system aware IC co‐design and verification entail early awareness of the impact of signal integrity, power integrity, timing, and electromagnetic interference (EMI) impact on functionality and performance. Higher frequencies, along with stringent EMC regulations, are driving the need for developing EMI‐aware design methodologies in early and sign‐off phases of design cycles. This article...
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