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We discuss key technologies of 180 nm-node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano-scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with MIM (metal-insulator-metal) capacitors. The key integration technologies in...
In order to realize a cost-effective high density FRAM product over 64-Mb, it is inevitable to develop technologies for a small cell and large wafer size without degradation during full integration. We have successfully demonstrated a fully functional 0.16 mum2 capacitor size, 64-Mb, 1T1C FRAM on an 8-inch wafer by introducing new integration technologies at 150 nm technology node. One of the key...
We have made great progress for mass production of a highly reliable 1.6V, 0.18 mum 1T1C FRAM embedded smart card. For mass production, our device has to pass standard qualification tests on the package level. These contain the infant life test (ILT), the high temperature operating life (HTOL), the endurance and the high temperature storage (HTS) test. Problems in the PZT capacitor integration scheme...
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