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This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two transistors connected in series with gates shortened, acting as a single device. The doping concentration of the two transistors in the structure is different, leading to higher threshold voltage of the transistor at the...
This paper presents the analog characteristics of asymmetric self-cascode SOI nMOSFETs biased in subthreshold region aiming at low power low voltage analog applications. It is shown for the first time that the advantages of this structure in comparison to single transistors and symmetric self-cascode is sustained below threshold and improves as device moves to subthreshold.
This paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.
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