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High-precision individual cell tuning was experimentally demonstrated, for the first time, in analog integrated circuits redesigned from a commercial NOR flash memory. The tuning is fully automatic, and relies on a write-verify algorithm, with the optimal amplitude of each write pulse determined from runtime measurements, using a compact model of cell's dynamics, fitted to experimental results. The...
We have modified a commercial NOR flash memory array to enable high-precision tuning of individual floating-gate cells for analog computing applications. The modified array area per cell in a 180 nm process is about 1.5 μm2. While this area is approximately twice the original cell size, it is still at least an order of magnitude smaller than in state-of-the-art analog circuit implementations. The...
A 45nm NOR flash technology featuring a self aligned contact ETOX architecture is demonstrated on a 1 Gbit MLC product having a die area of 30.05mm2. The cell size of 0.024μm2 is the smallest NOR cell reported to date and is manufactured entirely with dry lithography tools. With an aggressively scaled drain space of 100nm and gate length of 110nm, the cell shows robust short channel behavior, and...
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