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A 45nm NOR flash technology featuring a self aligned contact ETOX architecture is demonstrated on a 1 Gbit MLC product having a die area of 30.05mm2. The cell size of 0.024μm2 is the smallest NOR cell reported to date and is manufactured entirely with dry lithography tools. With an aggressively scaled drain space of 100nm and gate length of 110nm, the cell shows robust short channel behavior, and...
RTS noise is a growing issue in flash memory as the cell size scales down. By investigating NMOS and Ring devices, it is shown that noise induced by the STI edge dominates cell RTS/noise with scaling or after cycling. Device 1/f characterization highlights the drain STI edge as a critical area for RTS improvement in flash.
A highly manufacturable self-aligned contact ETOX?? NOR flash memory technology scalable beyond the 40nm node is presented. The technology has been demonstrated on an MLC-capable 256Mb array at the 65nm node with the smallest cell area (0.036??m2) reported to date. Key features include aggressively scaled drain space, symmetric S/D layout for superior lithography and device scaling, novel self-aligned...
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