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A novel region-based pixel digital architecture for latency buffering and trigger matching able to withstand extended trigger latencies and unprecedented data rates at the High-Luminosity LHC upgrade is presented. The architecture features above 99.5% efficiency at nominal 3 GHz/cm2 pixel hit rate and 1 MHz trigger rate with 12.5 μs trigger latency foreseen at HL-LHC. The overall inefficiency is dominated...
A low-power and low-noise synchronous front-end chain in a commercial 65 nm CMOS technology suitable for the future pixel upgrades at the CERN Large Hadron Collider (LHC) is presented. A shaper-less Charge-Sensitive Amplifier (CSA) with constant current feedback provides triangular pulse shaping for linear Time-over-Threshold (ToT) charge measurement. The sensor leakage current is compensated by the...
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