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This work presents a first common gate continuous time linear equalizer (CG-CTLE) with charge mode adaptation in 1.1 V, 65 nm CMOS technology. The proposed equalizer is realized with a common gate topology and offers an input impedance of 50 Ω. It also acts as a first stage of current modereceiver and is made adaptive to varying channel loss. Therefore, the need for an external...
With the reduction in feature size of CMOS transistors, the off-chip link speeds have not increased in the same pace as the on-chip link speeds. This gap in speed demands for better interface circuitry to mitigate the adverse effects of the off-chip links, especially, the intersymbol interference due to limited channel bandwidth and reflections due to impedance discontinuities. In this work, a first...
This work presents a new hybrid circuit topology for simultaneous bidirectional signaling over on-chip interconnects in a multi-channel signaling environment. The proposed hybrid circuit topology transmits the outbound signal and simultaneously receives the inbound signal from the combined sign al, which is a superposition of the outbound and inbound signals, thanks to the echo cancellation circuitry...
We propose a transceiver for an enhanced MIL-STD-1553 standard suitable for avionics and military applications. With the advancement in technology and increase in the resolutions of the sensors and other on board data sources, the amount of data to be processed and transferred has increased significantly. This necessitates the need for data rates greater than 1-Mbps. In this work, the transceiver...
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