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A MIPS 4Kc compliant embedded microprocessor design that incorporates architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-architectural level, and added instructions for error recovery. Soft-errors are detected as the instructions commit to...
An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via architectural, micro-architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to architectural state. Added instructions allow software controlled recovery and restart of upset instructions...
A MIPS 4Kc compliant embedded microprocessor core design that incorporates architectural features for software controlled radiation upset recovery is presented. The design uses fault tolerance techniques, i.e., error detection and instruction restart, implemented at the micro-architectural level, with architectural level changes, i.e., new instructions, for error recovery. Fine-grained, self-correcting...
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