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This paper introduces a new hardware efficient auto tuning for digitally controlled average current-mode (ACM) controllers. The auto-tuning procedure extracts the required coefficients of the ACM controller to achieve tight voltage regulation as well as closed-loop dynamic performance that may be defined by the end-user. System stability is facilitated for wide operation range under parameters uncertainties...
This paper introduces a fully-integrated 12-to-1.xV voltage regulator module IC. A fully synthesizable digital two-loop controller has been realized through HDL tools. Several new IP blocks have been developed: a window delay-line based ADC, two independent PI compensators with shared hardware for calculations, high-resolution digital PWM (HR-DPWM), and a programmable dead-time module. The mixed-signal...
This paper introduces a new plug-and-play transient suppression unit (TSU) to enhance the performance and reduce the overall volume of voltage regulator modules (VRMs). The TSU acts as an electronic capacitor that is realized by switched-capacitor technology, mimics an increased capacitance during load transients. The unit connects in parallel to any existing tightly-regulated power supply without...
This paper details efficiency analysis and characteristics of a gyrator resonant switched-capacitor converter (GRSCC) operating as a voltage regulator. Following the efficiency analysis, this paper introduces an optimal size-efficiency design procedure for IC realization of the converter. In area-sensitive applications, the optimization method combined with the converter's benefits present an attractive...
The paper presents a purely-digital architecture and an IC implementation of a PWM controller based on vendor's standard cells library alone. A full design flow is presented and explained. The architecture and configurations of the key building blocks are designed to meet the requirements of a complete digital implementation. The PWM controller is realized via Cadence tools in Tower Jazz 0.18μm power...
This paper presents the design and IC implementation of a fully-digital 10-bit, 4Mbps sampling rate, delay-line analog-to-digital converter (DL-ADC) for power management applications. The design of the ADC is based on the approach of delay cells string to reduce design complexity and the resultant the silicon area. A unique advantage of the new ADC architecture and the design process is that it is...
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