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The increasing use of machine learning algorithms, such as Convolutional Neural Networks (CNNs), makes the hardware accelerator approach very compelling. However the question of how to best design an accelerator for a given CNN has not been answered yet, even on a very fundamental level. This paper addresses that challenge, by providing a novel framework that can universally and accurately evaluate...
Most existing solutions to pipelining nested loops are developed for general purpose processors, and may not work efficiently for field-programmable gate arrays due to loop control overhead. This is especially true when the nested loops have nonrectangular iteration spaces (IS). Thus we propose a novel method that can transform triangular IS—the most frequently found type of nonrectangular IS—into...
Convolutional Deep Neural Networks (DNNs) are reported to show outstanding recognition performance in many image-related machine learning tasks. DNNs have a very high computational requirement, making accelerators a very attractive option. These DNNs have many convolutional layers with different parameters in terms of input/output/kernel sizes as well as input stride. Design constraints usually require...
IEEE 754 standard double precision (64-bit) binary floating point arithmetic unit is often necessary in complex digital signal processing applications. The basic operations, floating point addition and subtraction, need to be optimized to efficiently compute floating point multiplier, divider and square root. However, the main challenge is to design the floating point arithmetic unit hardware that...
This paper shows a new methodology to design hardware of 32-bit unsigned pipelined multiplier. The proposed hardware design is based on Finite State Machine (FSM) for reducing hardware resources and proliferating maximum frequency. Our suggested pipelined multiplier design contains only four 40-bit full adders to complete 64-bit 32 partial products addition. The synthesis report of the 32-bit pipelined...
This paper shows a new methodology to design the hardware for computing square root of N-bit unsigned numbers. The proposed hardware design is based on the modified non-restoring square root algorithm. Two different hardware designs, sequential pipeline architecture and asynchronous architecture for computing N-bit fixed point square root operation are proposed. The synthesis report of the designed...
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