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A CMOS digitally programmable analogue processor used in a neural network to linearize an NTC thermistor is presented in this paper. Particularly, the work focuses on the multiplier block and presents an alternative way to increase the weight resolution without oversizing the system. A neural network designed for linearization of the NTC thermistor is tested. Two architectures (the 8-bit and the proposed...
This paper presents an enhanced digital tuning approach for RC-active direct form circuits. By introducing a combined summing/dividing network for the current that flows from resistors to virtual grounds, an accurate frequency trimming is accomplished bringing out a linear dependence on the digital input code over a wide tuning range. Simulation results of a monolithic 12-bit 1.8 V–0.18 μm CMOS second...
A self-biased current buffer based on the quasi floating gate (QFG) approach to achieve class AB operation is presented in this paper. It was designed in standard 0.18μm CMOS process with 1.8V power supply. The buffer is able to copy an input current range of ±15μA with 8μA bias current. The total harmonic distortion (THD) remains below −84dB for 1 kHz frequency and maximum input current Ipp = 30pA...
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