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An analog-to-digital converter (ADC) for monitoring the voltages of a stack of eight Li-ion batteries is presented. The converted voltage range for each battery is 3–4.2 V with a maximum nominal input voltage of 33.6 V. High-voltage (HV) switches and a single HV capacitor make up the HV track and hold. The remaining part of the circuit operates at a nominal 5-V supply. An interleaved extended-range...
This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 µm2 and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of...
This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is...
This paper presents a novel architecture for capacitive sensor interfaces that is insensitive to electro magnetic interferers in hostile environments. A bridge structure, with a feedback control and a special band-pass filter, overcomes the problems that affect the standard approaches. Behavioural level simulations demonstrate the feasibility of the idea for 12-bit resolution.
Ultra high-speed comparators for data-converters operating with conversion rate of 10+ GS/s are discussed. It is shown that the use of nanometer technologies and specific architectures allow comparator speeds in the 30 ps range or below. State-of-the-art schemes of latch are critically analysed and strategies for enhancing the speed are discussed. A novel scheme, the latch with embedded preamp, increases...
A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation...
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