The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper we propose a low-complexity and high performance sum-of-sinusoid based architecture for the accurate simulation of Mobile-to-Mobile Rayleigh fading channels. Presented contributions concern the issues of designing and implementing a “double ring” Mobile-to-Mobile emulator, based on the Random Walk Process to reproduce accurately the behavior of the considered channel. Implementation...
A low-complexity and high performance configurable Double Rayleigh Mobile-to-Mobile fading channel emulator is proposed as well as its High Level Synthesis. The design and implementation of the proposed architecture based on a variant of the white Gaussian noise filtering method uses a minor hardware resource. The designed system is modeled using C/C++ high level language. Then the synthesis task...
This paper proposes a cascaded filter-based model that efficiently generates correlated complex Gaussian variates for mobile-to-mobile double-Rayleigh scattering multipath fading channels. We apply an infinite impulse response (IIR) filter followed by a variable interpolator, to accommodate different Doppler rates, can directly be applied to the design of so-called “double-Rayleigh” mobile-to-mobile...
This paper presents a new approach to design a Gaussian variate generator (GVG) circuit, based on the Box-Muller algorithm. The proposed GVG utilizes a double non-uniform segmentation combined with the use of CORDIC algorithm to reduce the block memory and to remove the hardware multipliers, respectively. These modifications result in a compact hardware which has a reduced resources occupation and...
Mathematical morphology operators are applied in many real time applications such as computer vision. Therefore, an efficient hardware implementation is needed to satisfy these real time requirements. In this paper we present an ASIP for basic morphological operations. We propose a modification of HGW algorithm to deal with the Plasma Soft Core processor. The ASIP has been synthesized into a FPGA...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.