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To obtain a 20cm-resolution image within a 15m distance using an X-band FMCW radar, an agile chirp frequency synthesizer phase-locked loop (FSPLL) with a wide chirp bandwidth (BW) greater than 750MHz and a short chirp period (Tm) less than 100µs is necessary. Challenges arise as one tries to realize a triangular chirp profile in Fig. 13.1.1 with a fast chirp slope (=BW/Tm) and precise linearity. In...
In this paper, a dual-band, frequency-modulated continuous-wave (FMCW) radar for short-range through-wall detection is proposed and implemented. This radar adopts a shared-aperture antenna technique for reducing antenna area and high-speed chirping to avoid flicker noise. It operates at the S-band (3 GHz) and the X-band (9 GHz), with 486 MHz chirp bandwidth and 860 MHz chirp bandwidth, respectively...
<?Pub Dtl?>A 9.2 GHz digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer function is presented. In other words, the closed-loop transfer function of the proposed digital PLL does not possess a closed-loop zero and the PLL achieves fast settling without exhibiting overshoots. While most previously reported peaking-free PLLs require additional circuit components which...
This paper describes a digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer. That is the PLL's second-order transfer function does not have a closed-loop zero. Such a PLL does not exhibit overshoots in the phase step response and achieves fast settling. Unlike the previously-reported peaking-free PLLs the proposed PLL implements the peaking-free loop filter directly in digital...
An all-digital DLL with 2-cycle lock time and 47-mUIpp jitter without dithering is presented. Implemented in 65nm CMOS, the DLL consumes only 1.3-mW at 1.6-GHz and occupies 0.016-mm2, making it suitable for low-cost clock deskewing and data alignment circuits in large-scale 3D ICs. A set of custom-designed, serially-connected control registers whose propagation delay is matched to that of the delay...
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