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An injection-locked frequency tripler with a push-push frequency doubler and a mixer core is demonstrated. The core power consumption of this design takes 5.34 mW. The locking range is from 13.5 GHz to 20.8 GHz. If concerning about the output power flatness, the acceptable frequency range is from 15.9 GHz to 17.1 GHz. The output power is −5 dBm. In addition, the harmonic suppression is −15 dB at least...
This paper presents a sub-harmonic injection-locked frequency tripler. This injection-locked frequency tripler was implemented with TSMC 0.18 μm 1P6M CMOS process. The feature of the proposed circuit employs the way of the dual-injection to lock the triple-frequency signal with higher output power. The available output power after the buffer stage of 0.6 dB gain is −2.88 dBm. The power consumption...
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