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A key advantage of asynchronous systems, in which the clock is re-placed by local handshaking signals between functional units, is their ability to operate correctly across a wide range of conditions including supply, temperature, aging and manufacturing variability. In this letter, we describe the design, simulation and layout of a representative example of a quasi-delay-insensitive asynchronous...
The natural pipelining behavior of Null Convention Logic (NCL) can often result in high speed data paths with fewer gate delays. However, the spanning completion detection and shared completeness path of the NCL handshaking signal may need very large completion detection gates that exhibit excessive fan-in, long propagation delays and high capacitance. Fine grained Two-Dimensional (2D) Pipelining...
This paper presents the comparison results of Area, Performance and Power of FIFO and Data-Queue on a logically determined Null Convention Logic RISC CPU register file Write-Back circuit. A shift register block implemented using Delay-Insensitive techniques operates in a way that is identical to a FIFO. In this paper, we illustrate the architectures of the Delay-Insensitive Asynchronous Data-Queue...
While asynchronous techniques are of increasing interest in low-power design, designers cannot simply transfer current synchronous techniques to that domain. In particular, commercial FPGA systems and their accompanying EDA tools are not well suited to asynchronous logic design. In this paper we describe and analyze five alternative description methods that allow Null Convention Logic (NCL) based...
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