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Chip-level Redundant Threading (CRT) is a generic approach employed in multi-core architectures to meet reliability or functional safety requirements of applications. Critical tasks are concurrently executed on several processing elements (PEs). Most approaches follow the fault detection and containment approach by employing a Sphere-of-Replication (SoR) on a fixed and hard-wired set of elements (PEs,...
Thread mapping is typically performed as an integral part of cooperative or pre-emptive operating system (OS) scheduling in order to share the processor core(s) among competing applications. Schedulers usually follow a single-objective performance optimization, such as maximizing core utilization or satisfying deadlines by the prioritization of threads. Meeting multiple orthogonal objectives, like...
This paper introduces a scalable hardware and software platform applicable for demonstrating the benefits of the invasive computing paradigm. The hardware architecture consists of a heterogeneous, tile-based manycore structure while the software architecture comprises a multi-agent management layer underpinned by distributed runtime and OS services. The necessity for invasive-specific hardware assist...
One of the major challenges of future many-core architectures is the efficient utilization of the abundance of computing power. Invasive computing provides a computing paradigm wherein applications can economically use the available compute resources. Applications can expand and shrink on demand depending on their thread level parallelism and resource availability. In this paper we present an analytical...
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