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A 60 GHz wideband power amplifier (PA) is fabricated in standard CMOS SOI 65 nm process. The PA is constituted by two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high resistivity SOI substrate. The PA measurements are carried out for supply voltages VDD going from 1.2 V to 2.6 V and achieve a saturation...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
This paper presents a new modeling method for integrated coplanar wave guides (CPW) and CPW discontinuities implemented in silicon on insulator (SOI) CMOS technology. Empirical equations, which are fitted to 3D EM simulations, are used to describe the electrical behavior of CPW as a function of the line's geometrical parameters. The models are validated through measurements up to 110 GHz. Thanks to...
Deep CMOS technology requires more and more accurate and robust RF CMOS models (PSP, BSIM, EKV...) for circuit design, predictable down to millimetrique wave range. Because of their scalability, these models are the more convenient ones, their major drawback being the huge number of parameters to experimentally extract, which is costly and time consuming. Hence, whenever CMOS technology is under development,...
This work focuses on the influence of the gate spacer offset width (Loffset) on SOI MOSFET high frequency (HF) properties. For this purpose, the DC simulated results were calibrated on experimental data of a 130 nm SOI partially depleted technology. Variations of Loffset were subsequently applied to study its impact on different HF figures of merit (ft, fmax)
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