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This study describes a low-power 16-bit logarithmic signal processor built using clocked adiabatic logic. The circuit has been designed and implemented using an Austria Micro Systems 0.35 μm complementary metal–oxide–semiconductor (CMOS) process. A test device has been fabricated and functionally verified. The processor architecture has an active area of 0.57 mm2. Simulation results with this architecture,...
This paper describes a 16-bit Logarithmic Signal Processor and its implementation using Clocked Adiabatic Logic (CAL). The proposed architectures for Lin2Log and Log2Lin converters are based on a linear interpolation algorithm. The CAL-Logarithmic Signal Processor has been designed using an AMS 0.35 µm CMOS process and consumes an area of 7.3 µm2. Spice simulations have shown that the circuit can...
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