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This paper describes an on-going work aiming at using FPGAs as a fast prototyping environment for Token-based Self-timed processors, inspired by the Octasic asynchronous design technique. Originally developed for Digital Signal Processing, this design technique is adapted here for an FPGA-based general purpose processor. The paper emphasizes improvements to existing FPGA implementation methodologies...
This paper describes a practical design method for protoyping self-timed processors using FPGAs. It adresses shortcomings of typical implementation strategies that use floorplanning to compensate for the lack of support of asynchronous designs in conventional FPGA tools. It is shown that a reported self-timed design technique can be used with a proposed set of constraints to make it fully compliant...
The conventional synchronous design approach is not suitable for implementing self-timed circuits on FPGAs. When design tools try to meet synchronous circuits timing constraints, they can violate self-timed setup timing constraints. This paper proposes a new methodology for implementing self-timed circuits in modern FPGAs using the Xilinx Hierarchical Design flow and a convenient architecture of a...
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