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Modeling the 3-D capacitances of FinFET devices, shown in Figure 1 [1], accurately is critical for the continuing scaling of CMOS nodes. Without accurate capacitance and process variation modeling, the yield of advanced nanometer CMOS nodes will decease due to high timing mismatch. In this paper, we propose a new process variation based characterization to enable R&D engineers to identify critical...
During the R&D of advanced nanometer CMOS technologies such as 20nm and beyond, we implemented in-house 3-D capacitance extraction software to provide R&D engineers with an accurate modeling tool to optimize the complex 3-D nanometer dimensions and materials that may be used for competitive CMOS devices in terms of power consumption, performance, and area. Our extractor solves 3-D Laplace's...
During the R&D of advanced nanometer CMOS technologies such as 20nm and beyond, we implemented in-house 3-D capacitance extraction software to provide R&D engineers with an accurate modeling tool to optimize the complex 3-D nanometer dimensions and materials that may be used for competitive CMOS devices in terms of power consumption, performance, and area. Our extractor solves 3-D Laplace's...
A UWB impulse radio (IR) timed-array radar using time-shifted direct-sampling architecture is presented. The transmitter array can generate and send a variety of 10GS/s pulses towards targets. The receiver array samples the reflected signal in RF domain directly by time interleaved sampling with equivalent sampling rate of 20 GS/s. The radar system can determine time of arrival (TOA) and direction...
To maximize the design efficiency of the test chip area and maintain the high accuracy measurement requirement of resistors and capacitors, a 4K-cells resistive and charge-base capacitive test structure array is designed for CMOS logic process development, monitor and model. The test chip utilizes 4-terminal (one of 4 is strongly grounded) Kelvin force/sense measurement for resistive-type and charge-base...
Dummy metal fills can cause systematic variations in capacitance and the impact on the parametric yields should be quantified rigorously. A new set of experimental nanometer circuit structures with close-to-reality dummy metal fills are designed and simulated using 3D electromagnetic field simulations and SPICE to quantify the impacts on the capacitance, the timing, and the crosstalk noise more realistically...
For sub-90nm technology nodes and below, random fluctuations of within-die physical process properties are also known as random on-chip variation (OCV). It impacts on the VLSI/SoC design yields significantly. This paper presents a recent silicon test chip experiment result which uses a set of innovative nanometer test structures and Monte-Carlo-based three-dimensional electromagnetic RC simulations...
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