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In order to meet the need for high-speed data processing, system designers have adopted Multi-Processor System-on-Chip (MPSoC) design. Network-on-chip (NoC) promises to be a viable solution as the basic communication fabric for such designs. A router is the basic component of NoC and using efficient internal blocks to design a router is expected to improve the performance of a router as a whole. One...
This paper present a comparison between the design of the 8T adder based Carry Select Adder (CSA) and 10T adder based CSA. Using both the designs of adders 4-bit CSA architecture has been developed and compared with the 28T adder 4-bit CSA. The 10T CSA design has reduced delay, power and area as compared with the 28T CSA with a slight tradeoff for area as compared to 8T CSA. The analysis shows that...
The paper gives a review of already existing 3-T XOR cells and provides an optimized value of (W/L) on the basis of simulation results obtained, so as to improve the threshold loss problems present in the existing designs of 3-T XOR cells thus helping improve the driving capability, however the driving capability is not sufficient for large circuits like multipliers, hence has a scope for further...
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