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This paper presents a 10-bit, 10MS/s pipelined ADC with a time-interleaved SAR. Owing to the shared multiplying-DAC between the flash ADC and the multi-channel-SAR ADC, the total capacitance of the SAR ADC is decreased by 93.75%. The proposed ADC architecture can therefore provide a higher resolution than the conventional time-interleaved flash-SAR ADC. The proposed 10-bit, 10 MS/s ADC achieves a...
In this paper high speed single output synchronous dc-dc boost converter is presented with type-III compensation network for power management in smart devices. Due to its quicker response time, it can handle load changes quickly as compared to other control techniques. Calculated phase margin and gain makes oscillation free output transient response. Input voltage is 1.8V, Inductance used is 600nH,...
In this paper we have presented a single inductor single output dc-dc synchronous boost converter using 5MHz switching frequency, ultimately reducing the inductor and capacitor sizes. Synchronous rectification has been employed. In the feedback loop we proposed a technique of smooth loop handover. For the dynamic load conditions we propose another technique to reduce ripples at higher loads. Control...
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